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Simple, Synchronous Voltage Mode PWM Controller
POWER MANAGEMENT Description
The SC2608 is a versatile voltage-mode PWM controller designed for use in step down DC/DC power supply applications. A simple, fixed frequency, highly efficient buck regulator can be implemented using the SC2608 with minimal external components. The input voltage range is from +3.3V to +12V. Internal level shift and drive circuitry eliminates the need for an expensive P-channel, high-side MOSFET. The small device footprint allows for compact circuit design. SC2608 features include temperature compensated voltage reference, triangle wave oscillator, current limit comparator, and an externally compensated error amplifier. Current limit is implemented by sensing the voltage drop across the bottom MOSFET RDS(ON). The SC2608 operates at a fixed frequency of 200kHz providing an optimum compromise between efficiency , external component size, and cost. SC2608 has a thermal protection circuit, which is activated if the junction temperature exceeds 150 OC.
SC2608
Features
+3.3V or +5V or +12V input voltage 200kHz operation High efficiency (>90%) 1% Reference voltage accuracy Hiccup mode over current protection Robust output drive RDS(ON) Current sensing for protection Industrial temperature range SO-8 package Integrated boot strap diode Thermal Shut down Fully WEEE and RoHS Compliant
Applications
Termination supplies Low cost microprocessor supplies Peripheral card supplies Industrial power supplies High density DC/DC conversion
Typical Application Circuit
SC2608
sense COMP/SS SENSE
+12V/+5V/+3.3V +12V
GND
VCC
DL
PHASE
DH
BST
VOUT sense
Figure 1
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SC2608
POWER MANAGEMENT Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
P a r a met er VCC to GND BST to PHASE BST to GND PHASE to GND DH to PHASE DL to GND
(note1) (note1)
Symb ol
M a xi m u m +20 +15 +35 -1 to +24 +15 -1 to +15 +7 +7
Un i ts V V V V V V V V
O
COMP/SS to GND SENSE to GND Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient Operating Temperature Range Storage Temperature Range ESD Rating (Human Body Model) JC JA TJ TSTG ESD
40 163 -40 to +125 -65 to +150 2
C/W C/W
O
O
C C
O
kV
Note 1: Under pulsing condition, the peak negative voltage can not be lower than -3.6V.
Electrical Characteristics
Unless specified: VCC = 12V, VBST - VPhase = 12 V, VOUT = 3.3V, TJ = TA = 25oC.
P a r a met er P ower Su p p l y Supply Voltage Supply Current E r r or A mp l i f i er E/A Transconductance Open Loop DC Gain Input Bias Current Output Sink Current Output Source Current O sci l l a t or Switching Frequency
Symb ol
C on d i t i on s
Mi n
Ty p
Ma x
Un i ts
VCC IC C VCOMP < 0.4V
4.5 6
14
V mA
Gm AO IFB ISINK ISOURCE VSENSE > 0.9V; VCOMP = 2.1V VSENSE < 0.7V; VCOMP = 2.1V
7 60 1 -700 120 3
mS dB uA uA uA
FOSC
Vcc =12V
2
180
200
220
kHz
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SC2608
POWER MANAGEMENT Electrical Characteristics
Unless specified: VCC = 12V, VBST - VPhase = 12 V, VOUT = 3.3V, TJ = TA = 25oC.
P a r a met er Ramp Peak Voltage Ramp Valley Voltage Maximum Duty Cycle M O SF E T D r i v er s DH Sink/Source Current DL Sink/Source Current DH Rise/Fall Time DL Rise/Fall Time Dead Time DL Minimum On Time Ref er en ce Sect i on Reference Voltage Temp Variance Line Variance C u r r en t L i mi t Trip Voltage Sof t - St a r t SS Source Current SS Sink Current U n d er v ol t a g e L ock ou t UVLO Threshold UVLO Hysterisis T h er ma l Sh u t d own Over Temperature Trip Point
Symb ol VP-K VV DMAX
C on d i t i on s 4.75V < VCC < 12.6V 4.75V < VCC < 12.6V 200kHz
Mi n
Ty p 1.8 0.8 90
Ma x
Un i ts V V %
ID H ID L tr, tf tr, tf tdt tON
tPW > 400nS VGS = 4.5V (src) VGS = 2.5V (snk) CL = 3000pF, See Fig. 2 CL = 4000pF, See Fig. 2 See Fig. 2 4.75V < Vcc < 12.6V
0.6 0.6
0.8 0.7 50 50 80 400
A
A ns ns ns ns
VREF VREF VREF
VCC = 12V -40 < TJ < +125 OC 4.75V < VCC <12.6V
0 .7 9 2 -1.5
0.8
0.808 1.5 4
V % mV
VTRIP
4.75V < Vcc < 12.6V Vtrip = VPHASE - GND
-190
-160
-130
mV
ISRC ISNK
VCOMP < 2.5V VCOMP > 0.5V
1.5 -1.5
uA uA
Vth Vhys
-40< TJ < 85OC -40< TJ < 85OC
4.1
4.3 200
4.5
V mV
TOTP
150
o
C
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SC2608
POWER MANAGEMENT Gate Drive Timing Diagram
Figure 2
Block Diagram
VCC
BST DH PHASE
OSC S + REF 0.8V R Q
LEVEL SHIFT
+
SENSE
-
0
COMP/SS
Figure 3
(c) 2005 Semtech Corp.
-
E/A
NON-OVERLAP TIMING
PWM
0
VCC OCP & UVLO
Vcc DL
OCP
GND
PHASE
+ -
0 0
4
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SC2608
POWER MANAGEMENT Pin Configuration
Top View
Ordering information
Device
(1)
Package SO-8 Evaluation Board
Temp Range (TJ) -40 to 125OC
BST DH GND DL
1 2 3 4
(8-Pin SO-8)
8 7 6 5
PHASE COMP/SS SENSE VCC
SC2608STRT(2) SC2608EVB
Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) This device is fully WEEE and RoHS Compliant
Pin Descriptions
Pin # 1 2 3 4 5 6 P i n N am e BST DH GN D DL VCC Sense COMP/SS PHASE Bootstrap for high side driver. High side driver outp ut. Ground. Low side driver outp ut. Chip bias sup p ly p in. Outp ut voltage sense inp ut. Error amp lifier outp ut. Connect comp ensation network to GN D. The comp ensation cap acitor serves as soft star t cap acitor. By p ulling this p in low will disable the outp ut. Connect this p in to the switching node between the MOSFETs. P i n Fu n c t i o n
7
8
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SC2608
POWER MANAGEMENT Theory of Operation
Synchronous Convert Synchronous Buck Conv er ter The output voltage of the synchronous converter is set and controlled by the output of the error amplifier. The inverting input of the error amplifier receives its voltage from the SENSE pin. The non-inverting input of the error amplifier is connected to an internal 0.8V reference. The error amplifier output is connected to the compensation pin. The error amplifier generates a current proportional to (Vsense - 0.8V), which is the COMP pin output current (Transconductance ~ 7mS). The voltage on the COMP pin is the integral of the error amplifier current. The COMP voltage is the non-inverting input of the PWM comparator and controls the duty cycle of the MOSFET drivers. The compensation network controls the stability and transient response of the regulator. The larger the capacitor, the slower the COMP voltage changes, and the slower the duty cycle changes. The non-inverting input voltage of the PWM comparator is the triangular ramp signal generated from the oscillator. The peak-to-peak voltage of the ramp is 1V, this is a parameter used in control loop calculation. When the oscillator ramp signal rises above the COMP voltage, the comparator output goes high and the PWM latch is reset. This pulls DH low, turning off the high-side MOSFET. After a short delay (dead time), DL is pulled high, turning on the low-side MOSFET. The oscillator also produces a set pulse for the PWM latch to turn off the low-side MOSFET, After a delay time, DH is pulled high to turn on the high-side MOSFET. The delay time is determined by a monostable on the chip. The triangle wave minimum is about 0.8V, and the maximum is about 1.8V. Thus, if Vcomp = 0.7V, high side duty cycle is the minimum (~0%) , but if Vcomp is 1.8V, duty cycle is at maximum ( ~90%).The internal oscillator uses an onchip capacitor and trimmed precision current sources to set the oscillation frequency to 200kHz. Figure 1 shows a 2.5V output converter. If the Vout <2.5V, then the SENSE voltage < 0.8V. In this case the error amplifier will be sourcing current into the COMP pin so that COMP voltage and duty cycle will gradually increase.If Vout > 2.5V, the error amplifier will sink current and reduce the COMP voltage, so that duty cycle will decrease.The circuit will be in steady state when Vout =2.5V , Vsense = 0.8V, Icomp = 0. The COMP voltage and duty cycle depend on Vin. remain in the off state whenever the supply voltage drops below the set threshold. Lockout occurs if VCC falls below 4.3V typ. Sof t Star t Soft Start The SC2608 provides a soft start function to prevent large inrush currents upon power-up or hiccup retry. If both COMP and SENSE pins are low (<300mV), the device enters soft start mode, and the compensation capacitor is slowly charged by an internal 1.5uA current source. When the COMP pin reaches 300mV, the low side FET is switched on in order to refresh the bootstrap capacitor, and begin PWM from a known state. As the COMP pin rises above 800mV, PWM begins at minimum duty cycle. COMP continues to charge, slowly sweeping the device through the duty cycle range until FB reaches the regulation point of 800mV. Once FB reaches the regulation point, the soft start current is switched off, and the strong error amp is enabled, providing a glitch-free entrance into closed loop operation. The overcurrent comparator is still active during soft start mode, and will override soft start in the event that an overcurrent is detected, such as startup into a dead short. R DS(ON) Current Limiting In case of a short circuit or overload, the low-side (LS) FET will conduct large currents. To protect the regulator in this situation, the controller will shut down the regulator and begin a soft start cycle later. While the LS driver is on,the Phase voltage is compared to the OCP trip voltage. If the phase voltage is lower than OCP trip voltage, an over current condition is detected. The low-side Rdson sense is implemented at end of each LS-FET turn-on duration. The minimum turn-on time of the LS-FET is set to be 400nS. This will ensure the sampled signal is noise free by giving enough time for the switching noise to die down.
OCP Hiccup In the event that an overcurrent is detected, the SC2608 latches the fault and begins a hiccup cycle. Switching is immediately stopped, and the drivers are set to a tristate condition (Both DH and DL are low). COMP is slowly discharged to 300mV with an internal 1.5uA current source, providing a long cooldown time to keep power dissipation low in the event of a continuous dead short. Once COMP and SENSE both fall below the 300mV threshold, the part Voltage Lockout U nder Voltage Lockout re-enables the 1.5uA soft start current , and the device begins The under voltage lockout circuit of the SC2608 assures a normal startup cycle again. that both high-side and low-side MOSFET driver outputs
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SC2608
POWER MANAGEMENT Applications Information (Cont.)
A note to the user is needed: The device cannot restart until both COMP and SENSE are low, to prevent start up into a charged output. In the event of an overcurrent condition, the output is quickly discharged by the load, therefore bringing SENSE below the 300mV threshold. If the COMP pin is pulled low by an external device (such as an open-drain logic gate used for system shutdown), and SENSE is high(above 300mV) is high while COMP is low, then the SC2608 turns on the low side FET to discharge the output before changing to shutdown or soft-start mode. The low side FET turns off when SENSE drops below 300mV and the converter remains in the tristate condition until COMP is released. Although this shutdown technique can be used successfully on the SC2608, the system designer using COMP for external shutdown will need to consider the load on the low side FET when discharging the output capacitor bank. For large capacitor bank, this peak current can be quite large as it is limited only by the RDS(ON) of the low side FET. Fortunately the duration of this event is quite short, and has been shown in the lab to have no detrimental effect on the performance of the external FETs. Disabling the output by pulling down COMP/SS pin is only recommended when the output capacitor bank is not too large. Compensation Network Design
G pwm =
1 Vramp
where the ramp amplitude is fixed at 1 volts. The total control loop-gain can then be derived as follows:
V 1 + sRcCo T (s ) = Gm * G pwm * Vin * bg * H c (s ) * V R L o 1 + s RcCo + + s 2 LCo 1 + c R Ro o
H c (s ) = 1 1 R+ 1 sC + sC i
The task here is to properly choose the compensation network for a nicely shaped loop-gain Bode plot. The following design procedures are recommended to accomplish the goal: (1) Calculate the corner frequency of the output filter:
Fo = 2
(2) Calculate the ESR zero frequency of the output filter capacitor:
Fesr = 1 2 R c C o
F SW 5
1 LC o
(3) Check that the ESR zero frequency is not too high.
F esr <
E/A
VBG 0.8V
G_PWM
L Rc VIN Ro
R Ci C
R1 R2
Co
Fig. 4. SC2608 small signal model.
The control model of SC2608 is depicted in Fig. 4. This model can also be used to generate loop gain Bode plots. The bandgap reference is 0.8V and trimmed to +/-1% accuracy. The desired output voltage can be achieved by setting the resistive divider network, R1 and R2. The error amplifier is transconductance type with fixed gain of:
Gm =
If this condition is not met, the compensation structure may not provide loop stability. The solution is to add some electrolytic capacitors to the output capacitor bank to correct the output filter corner frequency and the ESR zero frequency. In some cases, the filter inductance may also need to be adjusted to shift the filter corner frequency. It is not recommended to use only high frequency multi-layer ceramic capacitors for output filter. (4) Choose the loop gain cross over frequency (0 dB frequency). It is recommended that the crossover frequency is always less than one fifth of the switching frequency : 1 FX _ OVER = * FSW 5 If the transient specification is not stringent, it is better to choose a crossover frequency that is less than one tenth of the switching frequency for good noise immunity. The resistor in the compensation network can then be calculated as: when
V F F 1 R= * esr * X _ OVER * o F F Gpwm *Vin * Gm o esr Vbg
F sw 5
2
The compensation network includes a resistor and a capacitor in series, which terminates the output of the error amplifier to the ground. The PWM gain is inversion of the ramp amplitude, and this gain is given by:
0 . 007 A V
F o < F esr <
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SC2608
POWER MANAGEMENT Applications Information (Cont.)
(5) The compensation capacitor is determined by choosing the compensator zero to be about one fifth of the output filter corner frequency:
F zero
C=
An example is given below to demonstrate the procedure introduced above. Vin=12V Vo=2.5V Io=15A Fsw=200KHz L=2.2uH set Ci=1nF Rc=1.33K C=327.95nF for suitable soft start time set to Rc=1.5K set to C=100nF Co=4400uF Rc=0.009 Vbg=0.8V Vramp=1V Gm=0.007A/V
F =o 5
1 2R * Fzero
SC2608 soft start time is determined by the compensation capacitor. Capacitance can be adjusted to satisfy the soft start requirement. (6) The final step is to generate the Bode plot by using the simulation model in Fig. 4 or using the equations provided here with Mathcad. The phase margin can then be checked using the Bode plot.
100
Loop Gain Mag (dB)
50 mag( i) 0
50 10 100
1 .10
3
Fi
1 .10
4
1 .10
5
1 .10
6
0
Loop Gain Phase (Degree)
45 phase ( i)
90
135
180 10 100
1 .10
3
Fi
1 .10
4
1 .10
5
1 .10
6
Fig. 5. Bode plot of the loop
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SC2608
POWER MANAGEMENT
Typical Performance Characteristics
Vref vs. Temperature 0.83
Frequency vs. Temperature 210 Frequency(KHz) 200 190 180 170
0.82 Vref(V) 0.81 0.80 0.79 -50 -25 0 25 50 75 100 125 Temperature()
-50
-25
0
25
50
75
100
125
Temperature()
I_limit vs. Temperature 190 180
UVLO vs. Temperature 4.50 4.40 UVLO(V) 4.30 4.20 4.10
I_limit trip(mV)
170 160 150 -50 -25 0 25 50 75 100 125 Temperature()
-50
-25
0
25
50
75
100
125
Temperarure()
Icc vs. Temperature 4.0 3.7 Icc(mA) 3.4 3.1 2.8
Gate driver dead time vs. Temperature 100 Gate driver dead time(ns) 90 80 70 60 -50 -25 0 25 50 75 100 125 Temperature()
Soft start sourcing vs. Temperature 1.65 Soft start souring current(uA) 1.55 1.45 1.35 1.25 -50 -25 0 25 50 75 100 125 Temperature( )
UVLO_Hysteresis(mV) 200 150 100 50 0 -50 -25 0
-50
-25
0
25
50
75
100
125
Temperature()
UVLO_Hysteresis vs. Temperature
25
50
75
100
125
Temperature( )
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SC2608
POWER MANAGEMENT Application Information Typical Typical Application Schematic
+12V/+5V/+3.3V Q1 IP B 09N 03LA
C1 4 .7 u F /1 6 V
C2 1 5 00 u F /1 6 V
C3 1 5 00 u F /1 6 V
C4 1n
U1 8 7 Phase BST 1 2 3 4
R1 2R2 C5 1uF/16V L1 1.2uH R4 1R C12 2.2nF
1.6VOUT/20A Q2 IP D 06N 03LA R3 1K Sense R6 1K
2200uF /6.3V
2200uF /6.3V
4.7uF /6.3V
Sense +12V
SENSE GND VCC DL SC2608
5 R5 1R C13 1uF/16V
VOUT = 0.8V X (R3+R6)/R6
Bill of Materials
Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Qu an ti ty 1 2 1 2 1 2 3 1 1 1 1 1 1 2 2 1 Referen ce C1 C2,C3 C4 C5,C13 C6 C7,C8 C9,C10,C11 C12 L1 Q1 Q2 R1 R2 R3,R6 R4,R5 U1 Par t 4.7u F/16V 1500u F/16V 1n F/50V 1u F/16V 100n F/25V 2200u F/6.3V 4.7u F/6.3V 2.2n F 1.2u H IPD09N 03LA IPD06N 03LA 2R2 1.5K 1K, 1% 1R0 SC2608 Ven d er A ny Pan ason i c FJ A ny A ny A ny Pan ason i c FJ A ny A ny A ny In fi n eon In fi n eon A ny A ny A ny A ny SEMTECH
4.7uF /6.3V
6
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4.7uF /6.3V
R2 1.5k C6 100n
COMP/SS DH
C7
C8
C9
C10 C11
SC2608
POWER MANAGEMENT
Typical Performance Characteristics
Effic ie nc y V.S . Loa d C urre nt
92 90 88
Start up
Vin
Efficiency (%)
86 84 82 80 78 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Comp/ ss
DL VOUT
Loa d C urre nt (A)
Transient Response
Over Current Protection (33A DC tripped)
COMP/SS VOUT
VIN
Comp/ss DH
IL (10A/10mV)
VOUT
0 -18 A step load Gate waveforms OCP HICCUP
DH
VIN Comp/SS
Phase node
DH
DL
VOUT
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SC2608
POWER MANAGEMENT Application Information
Typical Typical DDR VDDQ Application Schematic
5VDual C4 1500uF /6.3V
Q1 R1 2.2R C5 330pF C7 220nF R2 5.1k 5VDual Sense U1 8 7 6 5 D1 BAT54H D2 D1N4148 +12V C15 1uF/16V Phase BST 1 2 3 4 C6 1uF/16V IP D 06N 03 LA
C1 4.7uF /16V
C2 1500uF /6.3V
C3 1500uF /6.3V
1.8VOUT/24A C10 1800uF /6.3V C11 4.7uF /6.3V C12 C13 4.7uF /6.3V 4.7uF /6.3V R3 1.27k Sense R5 1k
COMP/SS DH SENSE GND VCC DL SC2608
Q2 IP D 06N 03LA
L1 1.2uH/40A R4 2R2 C14 1n
C8 1800uF /6.3V
A ny A ny A ny A ny A ny A ny A ny A ny A ny A ny A ny A ny
C9 1800uF /6.3V
Bill of Materials
Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Qu an ti ty 4 3 1 2 1 3 1 1 1 1 1 1 2 1 1 1 1 Referen ce C1,C11,C12,C13 C2,C3,C4 C5 C6,C15 C7 C8,C9,C10 C14 D1 D2 L1 Q1 Q2 R1,R4 R2 R3 R5 U1 Par t 4.7u F/6.3V 1500u F/6.3V 330p F/50V 1u F/16V 220n F/25V 1800u F/6.3V 1n F/50V B AT54H 1N 4148 1.2u H/40A IPD06N 03LA IPD06N 03LA 2R2 5.1K 1.27K, 1% 1K, 1% SC2608 Ven d er
Pan ason i c FJ
Pan ason i c FJ
In fi n eon In fi n eon
SEMTECH
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SC2608
POWER MANAGEMENT Application Information
Typical Input Voltage Typical High In put Voltage Application Schematic
20VIN Q1 IPD13N03LA C1 4.7uF/25V C2 1000uF/25V L1 Q2 IPD13N03LA R4 2R2 C9 1n 2.2uH C6 2200uF/6.3V C7 4.7uF/6.3V C8 4.7uF/6.3V R5 5.25K Sense R7 1k
R1 0R C3 10pF/Opt. R3 Sense Vin R6 1KR/1206 U1 8 7 1K C5 100n 6 5 Phase BST 1 2 3 4 C10 2.2nF R2 5R1 C4 1uF/16V
5VOUT/8A
COMP/SS DH SENSE GND VCC DL SC2608
1KR/1206 R7
D1 8.2V
C11 1uF/16V
Bill of Materials
Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Q ua nti ty 1 1 1 2 1 1 2 1 1 1 1 1 1 1 1 2 1 1 2 1 Refer ence C1 C2 C3 C 4,C 11 C5 C6 C 7,C 8 C9 C 10 D1 L1 Q1 Q2 R1 R2 R3,R7 R4 R5 R6,R7 U1 Pa r t 4.7uF/25V 1000uF/25V 10pF/50V , O pt. 1uF/16V 100nF/16V 2200uF/6.3V 4.7uF/6.3V 1nF/50V 2.2nF/50V Zener 8.2V 2.2uH/15A IPD13N03LA IPD13N03LA 0R 5.1R 1 .K , 1 % 2R2 5.25K , 1% 1K R, 1206 SC 2608 Vender A ny Pa na soni c FJ A ny A ny A ny Pa na soni c FJ A ny A ny A ny A ny A ny Infi neon Infi neon A ny A ny A ny A ny A ny A ny SEMTEC H
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SC2608
POWER MANAGEMENT Outline Drawing - SO-8
D IM E N S IO N S M IL L IM E T E R S IN C H E S M IN N O M M A X M IN N O M M A X
.0 6 9 .0 1 0 .0 6 5 .0 2 0 .0 1 0 .1 9 7 .1 9 3 .1 5 7 .1 5 4 .2 3 6 B S C .0 5 0 B S C .0 1 0 .0 2 0 .0 4 1 .0 2 8 .0 1 6 (.0 4 1 ) 8 8 0 .0 0 4 .0 1 0 .0 0 8 .0 5 3 .0 0 4 .0 4 9 .0 1 2 .0 0 7 .1 8 9 .1 5 0 1 .3 5 0 .1 0 1 .2 5 0 .3 1 0 .1 7 4 .8 0 3 .8 0 1 .7 5 0 .2 5 1 .6 5 0 .5 1 0 .2 5 5 .0 0 4 .9 0 4 .0 0 3 .9 0 6 .0 0 B S C 1 .2 7 B S C 0 .2 5 0 .5 0 0 .4 0 1 .0 4 0 .7 2 (1 .0 4 ) 8 0 8 0 .1 0 0 .2 5 0 .2 0
A N 2 X E /2 E1 E e D
D IM
A A1 A2 b c D E1 E e h L L1 N 01 aaa bbb ccc
1 ccc C 2 X N /2 T IP S
2 e /2 B D
aaa C A2 S E A T IN G PLANE C bxN bbb A1 C A -B D GAGE P LA N E 0 .2 5 S E E D E T A IL S ID E V IE W
NO TES: 1. 2. 3.
A
h h
H
c
A
L (L 1 ) D E T A IL
01
A
C O N T R O L L IN G D IM E N S IO N S A R E IN M IL L IM E T E R S (A N G L E S IN D E G R E E S ). DATUM S -A AND -B T O B E D E T E R M IN E D A T D A T U M P L A N E -H -
D IM E N S IO N S "E 1 " A N D "D " D O N O T IN C L U D E M O L D F L A S H , P R O T R U S IO N S OR GATE BURRS.
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SC2608
POWER MANAGEMENT Land Pattern - SO-8
X
DIM
(C) G Z C G P X Y Z
DIMENSIONS INCHES MILLIMETERS
(.205) .118 .050 .024 .087 .291 (5.20) 3.00 1.27 0.60 2.20 7.40
Y P
NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.
2. REFERENCE IPC-SM-782A, RLP NO. 300A.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804 (c) 2005 Semtech Corp.
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